In integrated circuits comprising output stages destined to drive discrete power devices or themselves integrated on the same chip containing the drive and control circuitry, it is common to employ bootstrap capacitance so as to ensure a correct supply of the driving stage of the power device. In this type of system, it is essential to ensure the charge of the bootstrap capacitance in a very short period of time, and it is also common to use an LDMOS transistor in order to rapidly charge the bootstrap capacitance.
In the specific case of a driving circuit destined for a so-called High Side Driver (HSD), e.g., which conventionally forms a portion of a driving stage to drive a power device and which conventionally also connects to a so-called Low Side Driver (LSD) which in turn connects to ground (GND), the LDMOS should be able to charge the bootstrap capacitance when the HSD is tied to the low voltage, that is when the output of the HSD is low. By contrast, when the HSD is tied to the high voltage, that is when the HSD output is high, the LDMOS should represent a high impedance. These operating conditions must be complied with even during the high-to-low voltage phase of commutation (or viceversa) of the HSD itself regardless of possible current injections originating from charging and discharging processes of capacitances associated with the integrated structure of the LDMOS that must with stand the high voltage supply of the power device.
In order to control the intrinsic parasitic effects of an integrated LDMOS structure, it is a well known practice to realize the integrated structure represented by the circuit shown in FIG. 1. Typically, the driving voltage VG for the gate of the integrated LDMOS is obtained from the VS source voltage by means of a charging pump.
As a matter of example, the driving stage refers to an HSD that is driven in a turn-on or turn-off mode by a certain control signal IN. The HSD output is also connected to an LSD which, in turn, is connected to GND as understood by those skilled in the art. The HSD supply, when referred to high voltage (Vhv), is assured by the bootstrap capacitance Cboot which is connected to a load (LOAD) as illustrated and as understood by those skilled in the art. Moreover, during this phase, the bootstrap capacitance Cboot loses the electric charge necessary to the charging and consumption of the HSD.
During the phase where the output (OUT) of the HSD is low, the charging transistor LDMOS is turned on so as to restore the electric charge absorbed from the bootstrap capacitance Cboot in the preceding phase.
The n diodes (or forward biased diodes) have the specific function of impeding the turning-on of the parasitic PNP during the dynamic operation of the circuit. As a matter of fact, if the structure is dimensioned in such a way that Vboot&gt;VS=(n+1)Vbe, the parasitic transistor PNP can not turn on.
When turning on the circuit, and before commuting the HSD output, it is necessary to charge the initially uncharged bootstrap capacitance Cboot.
Referring back to the circuital scheme of FIG. 1, it can be noticed that when VS&gt;nVbe, the body node of the LDMOS transistor is at a voltage that satisfies the condition VB=VS-nVbe. If the voltage VS of the source node continues to rise faster than the voltage Vboot of the charging bootstrap capacitance, the parasitic PNP of the LDMOS integrated structure turns on, driving all or part of the current toward the integrated circuit substrate rather than in the Cboot capacitance. This implies the risk of not achieving the charging of the bootstrap capacitance or in any case to obtain this in an excessively long period of time with a considerable waste of energy via the substrate.
Additional and more serious inconveniences may occur during the HSD commutation with this known type of circuit. This is due to the presence of a parasitic NPN associated with the integrated structure of the LDMOS.
If we consider the presence of the junction capacitance Cbd between the body and the drain as shown in FIG. 2, during the voltage rising front of the drain node of the LDMOS transistor, a current injection in the body occurs through the Cbd capacitance of the body-drain junction.
If due to such a current injection the body potential VB rises above the value: VS+Vbe, by considering the design condition whereby: EQU Vboot&gt;VS-(n+1)Vbe (1)
the source-body junction is directly biased thus turning on the parasitic NPN transistor with the consequent destruction of the integrated component due to an extremely high power dissipation. This failure mechanism is very likely to occur since the body represents a high impedance node.